Ph.D.

Department of Computer Science and Engineering
The Chinese University of Hong Kong
Email: jiangbentian[at]gmail.com

Biography

I obtained my Ph.D. from the Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK) in 2021. My advisor was Prof. Evangeline F.Y. Young. Before that, I received my Bachelor Degree of Electronic & Information Engineering from Sichuan University (SCU). My research interests include datapath (computer arithmetic) optimization, RTL compilation, physical design and design for manufacturability in VLSI CAD (EDA).

My Resume/CV

Publications

Summary

• US patents (3), IEEE TCAD (CCF-A, 4), DAC (CCF-A, 4), ICCAD (CCF-B, 3), ASP-DAC (CCF-C, 2), ISPD (CCF-C, 1).

Journal Papers

• [J4] Lixin Liu, Tianji Liu, Bentian Jiang, Evangeline FY Young, “Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume: 43, Issue: 8, August 2024.

• [J3] Bentian Jiang, Xinshi Zang, Martin D.F. Wong and Evangeline F.Y. Young, “Exploring Rule-free Layout Decomposition via Deep Reinforcement Learning”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume: 42, Issue: 9, September 2023.

• [J2] Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, and Evangeline F.Y. Young, “Neural-ILT 2.0: Migrating ILT to Domain-specific and Multi-task-enabled Neural Network”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume: 41, Issue: 8, August 2022. [code]

• [J1] Bentian Jiang*, Jingsong Chen*, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, and Evangeline F.Y. Young, “CU.POKer: Placing DNNs on WSE with Optimal Kernel Sizing and Efficient Protocol Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume: 41, Issue: 6, June 2022.

Conference Papers

• [C10] Lin Shiju, Bentian Jiang, Weihua Sheng, and Evangeline Young, “Size-Optimized Depth-Constrained Large Parallel Prefix Circuits”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July, 2024.

• [C9] Qijing Wang, Bentian Jiang, Martin D.F. Wong and Evangeline F.Y. Young, “A2-ILT: GPU Accelerated ILT with Spatial Attention Mechanism”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 10-14, 2022.

• [C8] Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D.F. Wong and Evangeline F.Y. Young, “Partition and Place Finite Element Model on Wafer Scale Engine”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 10-14, 2022.

• [C7] Bentian Jiang, Xiaopeng Zhang, Lixin Liu and Evangeline F.Y. Young, “Building up End-to-end Mask Optimization Framework with Self-training”, ACM International Symposium on Physical Design (ISPD), Virtual Conference, March 21-24, 2021. [slides]

• [C6] Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu and Evangeline F.Y. Young, “Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization”, The 39th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Virtual Conference, Nov. 2-5, 2020. [slides] [code]

• [C5] Bentian Jiang*, Jingsong Chen*, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F.Y. Young, “CU.POKer: Placing DNNs on Wafer-Scale AI Accelerator with Optimal Kernel Sizing”, The 39th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Virtual Conference, Nov. 2-5, 2020 (* co-first authors). [slides]

• [C4] Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, and Evangeline F.Y. Young, “Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction”, The 38th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, Nov. 4-7, 2019. [slides] [code]

• [C3] Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F.Y. Young and Bei Yu, “FIT: Fill Insertion Considering Timing”, The 56th Annual Design Automation Conference (DAC), San Francisco, CA, USA, June 24–29, 2019. [slides] [poster]

• [C2] Bentian Jiang, Hang Zhang, Jinglei Yang and Evangeline F.Y. Young, “A Fast Machine Learning-based Mask Printability Predictor for OPC Acceleration”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan 21-24, 2019. [slides]

• [C1] Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F.Y. Young, “Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan 21-24, 2019. [slides] [code]

Patents

• [P3] Bentian Jiang, Natarajan Viswanathan, Zhuo Li, and Yi-Xiao Ding. “Machine-learning based clustering for clock tree synthesis”, U.S. Patent 11,645,441, issued May 09, 2023.

• [P2] Bentian Jiang, Natarajan Viswanathan, Zhuo Li, and Yi-Xiao Ding. “Machine-learning based prediction method for iterative clustering during clock tree synthesis”, U.S. Patent 11,244,099, issued February 08, 2022.

• [P1] Bentian Jiang, Natarajan Viswanathan, William Robert Reece, and Zhuo Li. “Dynamic weighting scheme for local cluster refinement”, U.S. Patent 11,188,702, issued November 30, 2021.

Tools

• Dr. CU [C1] [C4] (Evaluator of ICCAD 2019 Global Routing Contest)

• Neural-ILT [C6] [J2]

Honors & Awards

Talent Development Scholarship				HKSAR GSF						2021
DAC Young Fellow Award				DAC						2020
First Place Award at Contest on 'Wafer-Scale Deep Learning Accelerator Placement’				ISPD						2020
First Place Award at Contest on 'Initial Detailed Routing’				ISPD						2019
Second Place Award at Contest on 'Timing-aware Dummy Fill Insertion’				ICCAD						2018
Second Place Award at Contest on 'Initial Detailed Routing’				ISPD						2018
Full Postgraduate Studentship				CUHK						2017-2021
Excellent Graduate Award				SCU						2017

Experiences

• Principal Engineer | Huawei Hong Kong Research Center

  • On some interesting projects

  • Awardee of Individual Golden Medal Award (Highest individual award, Top 1%)

  • September 2021 – Now, Hong Kong SAR, CN

• Software Engineer Intern | Cadence Design Systems

  • Clock Tree Synthesis Team of Innovus

  • Advisor: Dr. Natarajan Viswanathan

  • April 2019 – September 2019, Austin, TX, USA

• Research Assistant | The Chinese University of Hong Kong

  • On fast lithographic hotspot detection

  • Advisor: Prof. Evangeline F.Y. Young

  • March 2017 – May 2017, NT, Hong Kong SAR, CN

Services

Technical Program Committee Member

• IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022

Journal Reviewer

• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

• ACM Transactions on Design Automation of Electronic Systems (TODAES)

• Integration, the VLSI Journal

Conference Reviewer

• IEEE/ACM Design Automation Conference (DAC)

• IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

• IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)

• International Symposium on Physical Design (ISPD)

Teaching

• 2020Spring: CENG4120 Computer-aided Design for Very Large Scale Integrated Circuits

• 2019Fall: CSCI3190 Introduction to Discrete Mathematics and Algorithms

• 2019Spring: CSCI1510 Computer Principles and C Programming

• 2018Fall: CSCI2510 Computer Organization

• 2018Spring: ENGG1110 Problem Solving By Programming